After the design of an integrated circuit (IC) or a system including multiple ICs, the design needs to be verified for correct operations. With the evolution of processing technologies and reduction of size and increase in complexity of devices, debugging of the complex circuit designs has become more and more difficult to perform using traditional simulation tools and techniques.
When an error is detected during debugging, designers may attempt to tap signals of interest from the circuit and use a logic analyzer to determine the cause of the error. However, this is a difficult process and is often not effective. Errors that have already occurred are often difficult to repeat and reconstruct. Therefore, it would be desirable to provide more efficient debugging capabilities.